A conventional manufacturing method of a semiconductor element uses a technique, in which, as shown in FIGS. 2(a) and 2(b), a through hole 61 and a wire groove are formed in an inter-layer insulating film 6 covering a bottom wire layer 7, so that a wire material is embedded therein.
As shown in FIG. 2(b), the inter-layer insulating film 6 has (1) a through hole area 23 which corresponds to the through hole 61, in which the inter-layer insulating film 6 is completely removed, and (2) a half area 22 in which the film thickness of the inter-layer insulating film 6 is reduced to approximately half in comparison with a surrounding area (which is referred to as a basic area 21, hereinafter). The half area 22 and basic area 21 form a step-wise shape 62 as shown in FIG. 2(a). The step-wise shape 62 is formed in the inter-layer insulating film 6 by a combination of prior arts, examples of which include the following two methods.
The first method is performed by means of half etching. In this method, as shown in FIG. 11(a), the half area 22 (see FIG. 2(b)) is exposed to light (indicated by arrows in the drawing) and developed on a wafer including a resist 5, the inter-layer insulating film 6, and the bottom wire layer 7, which are layered in vertical direction from top to bottom.
Next, as shown in FIG. 11(b), the half etching treatment is applied to the half area 22 from which the resist 5 has been removed when developed, and the inter-layer insulating film 6 is etched to approximately half the initial thickness, whereby the step-wise shape 62 is formed.
Next, as shown in FIG. 11(c), after the resist 5 is applied again, the through hole area 23 (see FIG. 2(b)) is exposed to light (indicated by arrows in the drawing) and developed. Then, as shown in FIG. 11(d), the etching treatment is applied to the inter-layer insulating film 6 in the through hole area 23, whereby the through hole 61 is formed.
The second method is performed by means of half exposure. In this method, half exposure to light (indicated by arrows in the drawing), by which the thickness of the resist 5 is reduced to approximately half the initial thickness, is effected on the half area 22 of a wafer of the identical structure as that shown in FIG. 11(a). Then, additional exposure is effected on the through hole area 23 to compensate an underexposure. Consequently, as shown in FIG. 12(b), a resist hole 101 and a resist step 102 are formed in the resist 5.
Then, as shown in FIG. 12(c), the inter-layer insulating film 6 in the through hole area 23 is removed by means of etching, whereby the through hole 61 is formed. Then, as shown in FIG. 12(d), the resist 5 in the half area 22 is removed (by means of ashing). Finally, as shown in FIG. 12(e), the step-wise shape 62 is formed in the inter-layer insulating film 6 by the half etching process.
Alternatively, available as a method of forming the step-wise shape 62 is a technique that employs an exposure and development process using a photomask furnished with transmittivity levels, in other words, a photomask having a blocking portion, a transflecting portion, and a transmitting portion.
Such a technique is disclosed in, for example, 1 Japanese Laid-open Patent Application No. 18351/1988 (Japanese Official Gazette, Tokukaisho No. 63-18351, published on Jan. 26, 1988), 2 Japanese Laid-open Patent Application No. 27636/1994 (Japanese official Gazette, Tokukaihei No. 6-27636, published on Feb. 4, 1994, and 3 Japanese Laid-open Patent Application No. 49410/1995 (Japanese Official Gazette, Tokukaihei No. 7-49410, published on Feb. 21, 1995).
In the technique of the disclosure 1, a translucent film made of chromium oxide (CrO) is used as the transflecting portion, and a chromium (Cr) film is used as the blocking portion. In the technique of the disclosure 2, a silicon dioxide film mixed with a light-absorbing material is used as the transflecting portion, and a triple-layer blocking film having a structure of chromium oxide/chromium/chromium oxide (CrO/Cr/CrO) is used as a blocking film. Further, in the technique of the disclosure 3, the blocking portion and transflecting portion are formed in the photomask made of a chromium compound by giving different thicknesses to the chromium compound film.
However, each of the foregoing techniques has the following problems.
The first method as a combination of prior arts is popular, but a series of processes, including the resist apply process, exposure and development process and etching process, has to be repeated twice. Thus, this method involves quite a large number of processes. For this reason, not only throughput, but also yield of devices is reduced, because dust adheres to the semiconductor element more frequently.
In the second method, the exposure and development process has to be repeated twice, but the other processes are performed only once, thereby involving fewer processes in comparison with the first method. However, because two photomasks are used in the exposure and development process, the exposure pattern of the half area 22 and that of the through hole area 23 have to be aligned accurately.
The accuracy of alignment of the exposure patterns is determined by accuracy of alignment of each photomask by means of a stepper and accuracy of relative positions of the two photomasks with respect to each other (overlapping accuracy of the photomasks). Because each accuracy has to be quite high, the accuracy of alignment can be a de-stabilizing factor in the exposure and development process.
As has been discussed, the foregoing methods demand repetitive exposure and development or highly accurate alignment of the photomasks, which complicates a process of forming the step in the inter-layer insulating film 6.
In contrast, the techniques in the disclosures 1 through 3 use a single photomask including the transflecting portion in addition to the blocking portion and transmitting portion. Hence, the resist step 102 as shown in FIG. 12(b) can be formed in the resist 5 by effecting exposure and development once. Consequently, the step-wise shape 62 can be formed in the inter-layer insulating film 6 without repeating exposure and development or aligning the photomasks accurately, thereby shortening and simplifying the step forming process.
However, as far as a specific arrangement of the transmitting portion and transflecting portion formed in a single photomask is concerned, the techniques in the disclosures 1 through 3 teach the transmittivity levels, but remain silent about giving a phase difference to the transflecting portion with respect to the transmitting portion.
The through holes 61 and wire grooves formed in the semiconductor element are so minute that, in order to transfer such a minute exposure pattern accurately onto the resist 5 through the photomask having the transmittivity levels, a phase difference of the transflecting portion with respect to the transmitting portion has to be controlled. For this reason, the techniques in the disclosures 1 through 3 share a problem that the resist step 102 can not be formed in the resist 5 as desired in a reliable manner.